1. Field of the Invention
This invention relates to a semiconductor memory device, such as an EPROM or a mask ROM, making use of a current-to-voltage conversion type sense amplifier.
2. Description of Related Art
A memory device, such as an EPROM or a mask ROM, usually has its memory cells constituted by MOS transistors. In each memory cell, data to be stored, such as "0" or "1" are determined as a function of the threshold voltage of the MOS transistor. The MOS transistor constituting the memory cell has its drain and source connected to a bit line and a grounding line, respectively. The data stored in the memory cell are read out as the magnitude of the electric current flowing in the bit line.
FIG. 1 is a circuit diagram showing a sense amplifier and related circuitry of a conventional EPROM. A power supply voltage Vcc is supplied to a sense node 1 by means of a pMOS transistor 7 as a load, and the voltage at the sense node 1 is amplified by three stage inverters 2, 5 and 6. A current path across input and output terminals of the inverter 2 is rendered electrically conductive by a pMOS transistor 3 and an nMOS transistor 4 which together precharge the sense node 1. An nMOS transistor 8 and an inverter 9 function to limit the bit line voltage and, when the input terminal voltage of the inverter 9 is shifted to higher than a threshold voltage, the nMOS transistor 8 is turned off. The bit line is connected to an input terminal of the inverter 9 by means of a Y-selecting transistor 10. To the bit line are connected MOS transistors 12, 13, . . . each constituting a memory cell. Selection signals .phi.X1, .phi.X2, . . . are supplied to the MOS transistors 12, 13, . . . , respectively, while a selection signal .phi.Y is supplied to the Y-selecting transistor 10. The number of the Y-selecting transistors and the number of the MOS transistors constituting the memory cells are determined in dependence upon the size of the memory cell array, although only a few of these MOS transistors are shown for simplicity. A MOS transistor 11 is a precharging transistor which, when turned on, precharges the bit line.
The readout operation of the EPROM is effectuated by amplification by the inverters 2, 5 and 6. High-speed sensing becomes possible because the electrical potential at the sense node 1 already differs at the precharging stage as a function of data stored in the memory cell. Turning to FIGS. 2 and 3 showing voltage changes at the sense node 1, FIG. 2 shows voltage changes when a directly preceding data is in the erasure state and FIG. 3 shows voltage charges when a directly preceding data is in the program or write state. If, as shown in FIG. 2, the directly preceding data is in the erased state, and the current cell or the accessed cell is the programmed cell, the voltage changes describe a curve R.sub.1. If the current cell is in the erased state, the voltage changes describe a curve R.sub.2. If, as shown in FIG. 3, the previously stored contents are in the programmed state, and the current cell is in the programmed state, the voltage changes describe a curve R.sub.3 and, if the current cell is in the erased state, the voltage changes describe a curve R.sub.4. As shown in FIGS. 2 and 3, the time until time point T.sub.1 is the precharging period, for the present EPROM, such that, during the time until the time point T.sub.1, when the MOS transistors 3 and 4 are turned on and the input and the output of the inverter 2 are shorted, a sufficient voltage difference cannot be developed. However, during the precharging period, a voltage difference .DELTA.Vm, which is a function of the data in the MOS transistor to be accessed, already appears at the sense node. This voltage difference .DELTA.Vm is produced in dependence upon the relative magnitude of a current I.sub.L flowing in the pMOS transistor 7 as a load and a current current I.sub.CELL flowing through the MOS transistors 12, 13 . . . as memory cells. Since the voltage difference .DELTA.Vm is already produced at the precharging time point as a function of the data stored in the memory cells, high-speed sensing may be realized with the present EPROM.
However, the following problems are raised with the circuit shown in FIG. 1.
Taking the case in which, as an example, the source voltage Vcc is fluctuated from 5.5 V to 4.5 V. If the source voltage is 5.5 V and the cell accessed at a directly preceding time is in the programmed state, the bit line voltage is equal to a precharging voltage, such as 1.3 V, conforming to 5.5 V, which precharging voltage is higher than a precharging voltage, such as 1.15 V, conforming to 4.5 V. If the source voltage is changed to the lower value of 4.5 V, the bit line is in the overcharged state. Due to the bit line overcharging, the nMOS transistor 8 controlled by the inverter 9 is turned off, as a result of which the voltage at the sense node 1 is maintained at the higher value.
FIG. 4 shows the voltage at the sense node 1 during bit line overcharging. In case of overcharging, discharging occurs almost exclusively through the memory cell. Thus the bit line is kept in the overcharged state, so that, during a time interval T.sub.EX, the nMOS transistor 8 is kept in the off state. With the cell current of 70 .mu.A, a bit line capacity of 8 pF and an equilibrium bit line voltage difference of 0.15 V, as an example, the delayed time interval T.sub.EX caused by excess bit line charging is of the order of 17 ns. After time interval T.sub.EX, the voltage at the sense node 1 proceeds as shown by a curve R.sub.4 in FIG. 3. The operation of the inverters 2, 5 and 6 is started at time T.sub.1. It is after lapse of the time T.sub.SO following the time interval T.sub.EX that data are ultimately read out from the sense amplifier. The reason is that, because of the limited driving capability of the inverters 2, 5 and 6 during the period until time point T.sub.1, it takes a lot of time before the sense node output, which has been kept at a lower level conforming to the high sense node level during the time interval T.sub.EX, is increased to an output level conforming to the sense node level at time point T.sub.1. Thus the circuit of FIG. 1 has a defect that the readout time is prolonged as a result of bit line overcharging.
On the other hand, the circuit shown in FIG. 1 is affected by noise superposition. That is, if noise is superposed at the sense node 1, as shown in FIG. 5 the inverter 2 responds quickly at a peak P.sub.1 so that the output voltage of the inverter 2 is lowered considerably. Since the driving capability of the inverter 2 itself remains low after peak P.sub.2, the output voltage of the inverter 2 is returned to its original value only with a time lag.